1. Field of the Invention
The present invention relates to a semiconductor memory and in more specific terms, it relates to a semiconductor memory provided with a decoder circuit having a redundancy relief function.
2. Description of the Related Art
A semiconductor memory such as a DRAM is normally provided with a column redundancy circuit that employs an ATD (address transition detector) or a shift-type redundancy circuit, to achieve an improvement in the yield. Of the two types of redundancy circuits, the shift-type redundancy circuit can be achieved through a simpler circuit structure compared to a column redundancy circuit employing an ATD and does not require as much time for the column line to enter an active state.
A semiconductor memory provided with a shift-type redundancy circuit is explained below in reference to FIG. 6. The semiconductor memory in the prior art, which constitutes a DRAM, includes a column decoder circuit CD1, a memory cell sub-array MCA and a sense amplifier sub-array SAA The shift-type redundancy circuit constitutes part of the column decoder circuit CD1.
The memory cell sub-array MCA is provided with a plurality of memory cells MCij (i=0, 1, . . . , j=0, 1, . . . , 255). The individual memory cells MCij are connected to a plurality of word lines WL(0), WL (1), . . . , WL(i), . . . , and the plurality of complementary bit line pairs BL(0)/BLb(0), BL(1)/BLb(1), . . . , BL(j)/BLb(j), . . . , BL(255)/BLb(255), and are arranged at individual points of intersection in a matrix.
Each memory cell MCij constitutes a so-called 1-transistor memory cell comprising an N-type transistor (not shown) and a capacitor (not shown) with the gate, the drain and the source of the N-type transistor respectively connected with the word line WL(i), the bit line BL(j) and one end of the capacitor. At the other end of the capacitor constituting each memory cell MCij, a voltage at a level that is halfway between the source voltage Vcc of the DRAM and the substrate voltage Vss is applied.
The sense amplifier sub-array SAA located adjacent to the memory cell sub-array MCA is provided with a plurality of sense amplifiers SA(0), SA(1), . . . , SA(255) and a plurality of data transfer circuits DT(0), DT(1), . . . , DT(255). The bitline pair BL(j)/BLb(j) is connected to a data transfer circuit DT(k) via a sense amplifier SA(k) (k=0, 1, . . . , 255), and the data transfer circuit DT(k) is further connected with a data bus pair LDB/LDBb and a column line CL(k).
The operation achieved in the DRAM constituting the semiconductor memory in the prior art illustrated in FIG. 6 is now explained. When the word line WL(i) is selected, data that are stored as an electrical charge at the memory cell MCij connected to the word line WL(i) are output to the bit line BL(j), thereby generating a potential difference at the bit line pair BL(j)/BLb(j). The sense amplifier SA(k) detects the potential difference at the bit line pair BL(j)/BLb(j) and amplifies the potential difference.
If the column line CL(k) is selected by the column decoder circuit CD1 and is set to the source voltage Vcc, the data transfer circuit DT(k) connected with the column line CL(k) enters an ON state, and the bit line pair BL(j)/BLb(j) and the data bus pair LDB/LDBb become electrically continuous. As a result, the data amplified by the sense amplifier SA(k) are transferred to the data bus pair LDB/LDBb. Thus, a data read operation from the MCij is achieved. It is to be noted that the DRAM in the prior art illustrated in FIG. 6 is provided with an auxiliary column line CLr.
Next, the structure of the column decoder circuit CD1 is explained in reference to FIG. 7. The column decoder circuit CD1 is provided with fuse blocks FB(0), . . . , FB(k), FB(k+1), . . . , FB(255), decoders D(0), . . . , D(k), D(k+1), . . . , D(255), redundancy control circuits RL(0), . . . , RL(k), RL(k+1), . . . , RL(255) and RLr, column line drivers DV1(0), . . . , DV1(k), DV1(k+1), . . . , DV1(255) and DV1r, a fuse driver FDV and a pre-charge circuit PC.
The fuse block FB(k) is provided with two fuses FU0(k) and FU1(k) that are independent of each other. The fuse FU0(k) and the fuse FU1(k) are connected to the redundancy control circuit RL(k) via a fuse node F0(k+1) and a fuse node F1(k+1) respectively. In addition, the fuse FU0(k) and the fuse FU1(k) are respectively connected to a fuse FU0(k+1) and a fuse FU1(k+1) in the adjacent fuse block FB(k+1) via the fuse node F0(k+1) and the fuse node F1(k+1). As a result, the fuses FU0(0).about.FU0(255) and FU1(0).about.FU1(255) in the fuse blocks FB(0).about.FB(255) are connected in series along the direction in which the word lines WL extend over the entire column decoder circuit CD1.
The decoder D(k) is constituted as a 4-input NAND gate to which input column address signals PY76, PY53, PY21 and PY0 are input. The output terminal of the decoder D(k) is connected to the redundancy control circuit RL(k) and also to the adjacent redundancy control circuit RL(k+1), so that an output signal YD(k+1) output by the decoder D(k) is input to the redundancy control circuits RL(k) and RL(k+1). The input column address signals PY76, PY53, PY21 and PY0 are pre-decoded signals. The input column address signal PY76 is a signal achieved by pre-decoding addresses 6 and 7 and has a 4-bit width. The input column address signal PY53 is a signal achieved by pre-decoding addresses 3.about.5 and has an 8-bit width. The input column address signal PY21 is a signal achieved by pre-decoding addresses 1 and 2 and has a 4-bit width. The input column address signal PY0 is a signal achieved by pre-decoding address 0 and has a 2-bit width. For instance, the lowest order bit among the four bits of the input column address signal PY76 is input to the decoders D(0), D(4), D(8), . . . , D(252), the second bit maybe input to the decoders D(1), D(5), D(9), . . . , D(253), the third bit is input to the decoders D(2), D(6), D(10), . . . , D(254) and the highest-order bit is input to the decoders D(3), D(7), D(11), . . . , D(255). Likewise, the individual bits in the input column address signals PY53, PY21 and PY0 are sequentially input to the decoders D(0).about.D(255). In this structure, a single decoder D(k) corresponding to the column address is selected. It is to be noted that in the following explanation, a pre-decoded signal is referred to as an input column address signal.
The redundancy control circuit RL(k-1) (not shown), the redundancy control circuit RL(k) and the redundancy control circuit RL(k+1) are arranged over multiple stages along the direction in which the word lines WL extend, with redundancy selection signals RE(k) and REb(k) output by the redundancy control circuit RL(k-1) input to the redundancy control circuit RL(k) and redundancy selection signals RE(k+1) and REb(k+1) output by the redundancy control circuit RL(k) input to the redundancy control circuit RL(k+1). The redundancy control circuit RL(k) is connected with the column line driver DV1(k) which drives the column line CL(k) via a node DEC(k). Redundancy selection signals RE(0) and REb(0) input to the redundancy control circuit RL(0) are respectively set to the substrate voltage Vss and the source voltage Vcc.
Redundancy selection signals REr and RErb output by the redundancy control circuit RL(255) and an output signal YDr from the decoder D(255) are input to the auxiliary redundancy control circuit RLr. The redundancy control circuit RLr is connected to the column line driver DV1r that drives the auxiliary column line CLr via a node DECr.
The pre-charge circuit PC is connected to the fuse block FB(255) which corresponds to the column line CL(255) via fuse nodes F0c and F1c. The pre-charge circuit PC charges of the fuses FU0(0).about.FU0(255) and the fuses FU1(0).about.FU1(255) to the level of the source voltage Vcc when the levels of the input row address signals PX0 and PX1 are at the substrate voltage Vss.
The input row address signals PX0 and PX1 are input to the fuse driver FDV which is provided adjacent to the fuse block FB(0) corresponding to the column line CL(0). The output of the fuse driver FDV is connected to the fuse block FB(0) via fuse nodes F1(0) and F0(0). The fuse driver FDV sets the fuses FU0(0).about.FU0(255) to the substrate voltage Vss if the level of the input row address signal PX0 is at the source voltage Vcc, and sets the fuses FU1(0).about.FU1(255) to the substrate voltage Vss if the level of the input row address signal PX1 is at the source voltage Vcc.
Next, the redundancy relief operation performed to correct a column line failure in the DRAM in the prior art is explained. FIG. 8(a) shows the column decoder circuit CD1 with all the column lines CL(0).about.CL(255) operating in a normal state, and FIG. 8(b) illustrates the column decoder circuit CD1 with the column line CL(k) having an failure. In order to facilitate the explanation, the redundancy control circuits RL(0).about.RL(255) are schematically shown as switches SW(0).about.SW(255) respectively in the figures.
When all the column lines CL(0).about.CL(255) are operating in a normal state, the fuses FU0(k) and the fuses FU1(k) in the fuse blocks FB(0).about.FB(255) are not disconnected, and, as illustrated in FIG. 8(a), all the switches SW(0).about.SW(255) are connected to the N terminals. Consequently, the output signals YD(0).about.YD(255) output by the decoders D(0).about.D(255) are respectively provided to the column lines CL(0).about.CL(255).
If, on the other hand, there is a failure at the column line CL(k) and the other column lines CL(0).about.CL(k-1) and CL(k+1).about.CL(255) are operating in a normal state, the fuse FU0(k) in the fuse block FB(k) is disconnected, and as illustrated in FIG. 8(b), the switches SW(0).about.SW(k-1) are connected to the N terminals with the switches SW(k).about.SW(255) connected to the R terminals. As a result, the output signals YD(0).about.YD(k-1) output by the decoders D(0).about.D(k-1) are respectively provided to the column lines CL(0).about.CL(k-1), the output signals YD(k).about.YD(254) output by the decoders D(k).about.D(254) are respectively provided to the column lines CL(k).about.CL(255) and the output signal YD(255) output by the highest-order decoder D(255) is provided to the auxiliary column line CLr. Thus, the decoders in the higher-orders, starting with the decoder D(k), i.e., the decoders D(k).about.D(255) are shifted upward by one order to be connected to the column lines CL(k+1).about.CL(255) and the auxiliary column line CLr instead of the originally corresponding column lines CL(k).about.CL(255), thereby achieving redundancy relief for the failure at the column line CL(k).
In the semiconductor memory in the prior art, in which the column decoder circuit CD1 is provided with the same number offuse blocks FB(0).about.FB(255) as the number of the column line drivers DV1(0).about.DV1(255) with the fuse blocks and the column line drivers arranged in a single row along the direction in which the word lines WL extend as illustrated in FIG. 7, the pitch of the fuse blocks FB(0).about.FB(255) and the pitch of the column line drivers DV1(0).about.DV1(255) are equal to each other. In addition, since the pitch of the column line drivers DV1(0).about.DV1(255) is equal to the pitch of the column lines CL(0).about.CL(255), the fuse blocks FB(0).about.FB(255) and the column lines CL(0).about.CL(255) in the semiconductor memory in the prior art are laid out at the same pitch.
If the memory cell size is to be reduced and the layout pitch is to be shortened in order to achieve a larger capacity and higher integration in a semiconductor integrated circuit in the prior art, it becomes necessary to reduce the pitch of the column lines CL(0).about.CL(255) accordingly, which, in turn, results in a reduction in the pitch of the fuse blocks FB(0).about.FB(255). However, in order to disconnect the fuses FU0(k) and FU1(k) in the fuse block FB(k) in a stable manner by employing a laser repair apparatus or the like, for instance, a considerable distance must be allowed between the fuse block FB(k) and the adjacent fuse blocks FB(k-1) and FB(k+1). In other words, as a larger capacity and higher integration are achieved in the semiconductor memory in the prior art, a failure tends to occur more often when disconnecting a fuse, which poses a concern of a poor product yield.
In addition, in the redundancy relief achieved by the column decoder circuit CD1 in the semiconductor memory in the prior art, if there is a failure at the column line CL(k), for instance, the column line CL(k) is replaced by the adjacent column line CL(k+1). However, if two adjacent column lines CL(k) and CL(k+1) fail, redundancy relief cannot be achieved.